In various digital systems, signals can be transmitted from a transmitter to a receiver via a transmission channel. The transmission channel may be any suitable wired (or wireless) medium which links the transmitter to the receiver. However, in many instances (e.g., high data transmission speeds), the transmission channel becomes lossy. The transmission losses can be a result of, among other things, interference, attenuation, and delay in the channel. Further, such losses can also have considerable detrimental effect on the transmitted signal by the time it reaches the receiver. For example, sufficient amplitude and phase distortion of the transmitted signal may result in intersymbol interference (ISI) in the signal received at the receiver. ISI generally refers to the ‘smearing’ of a pulse or other symbol representing the logic state of one data bit to the degree such that it contributes to the content of one or more of the preceding (i.e., pre-cursor ISI) or succeeding (i.e., post-cursor ISI) data bits.
To guard against such detrimental effects, many serial receiver systems may perform at least one of decision feedback equalization (DFE) or continuous time linear equalization (CTLE) on the received data. Such serial receiver systems may include (i) an analog front end that provides some CTLE, (ii) a sampler, a (iii) DFE that uses the quantized receive data to adaptively feedback a correction signal, and (iv) a timing recovery unit. The timing recovery unit may use edge samples of the signal to determine if the received timing is early or late (i.e., phase detection). This information may go to a digital loop filter, which outputs to a phase interpolator in order to generate a recovered clock. The recovered clock includes an in-phase (I) and quadrature (Q) component. The I and Q clocks are expected to be perfectly in quadrature (i.e., the clocks are offset from each other by ninety degrees). The I and Q clocks are used to sample (i.e., with the sampler) the input signal and process the received data. Specifically, by lining the Q clock up with the edge of the received data bit, the I clock can be used to sample the center of the data bit. Further, in order to effectively sample the incoming data, the I clock should be at the same frequency as the incoming data. Generally, the frequency of the I clock and the incoming data is determined and provided by one or more crystal oscillators. If the I clock and the received data are associated with the same crystal oscillator, the frequencies for the I clock and the received data are likely also the same. However, in many instances, the crystal oscillators are different. In this case, even if the crystal oscillators are calibrated to the exact same frequency, for a myriad of reasons (e.g., mechanical differences in the respective crystals), the frequencies are not exactly the same but, rather, are almost synchronous (i.e., plesiochronous). For example, the crystal oscillators may be off by a couple hundred parts per million. In order to overcome this frequency offset, the phase interpolator gradually modifies the phase of the I and Q clocks so that they keep up with the frequency of the received data. For instance, if the crystal oscillator associated with the received data is running a little bit faster than the crystal oscillator associated with the I and Q clocks, the phase interpolator will advance the phase of the I and Q clocks to overcome the difference. Specifically, the phase interpolator gradually advances (i) the phase of the Q clock to align with the edge of the data bit and (ii) the phase of the I clock to align with the center of the data bit. Ideally, the quadrature relationship between the I and Q clocks should be maintained as the phase interpolator(s) strives to overcome the frequency offset. Unfortunately, due to certain non-linearity characteristics of the phase interpolator (e.g., integral non-linearity), the I and Q clocks don't perfectly align with each other. Specifically, because the phase interpolator interpolates an output clock (e.g., I or Q clock) between two inputs clocks, there are always some phase steps that are slightly different than others, and, as a result, the phase relationship between the I and Q clocks may vary. Accordingly, over time, as the phase interpolator attempts to align the Q clock to the edge of the data bit, the I clock may dither (e.g., jitter) around the center of the data bit. For example, instead of remaining at ninety (90) degrees (i.e., quadrature) from the edge of the data bit, the I clock can rotate between ninety-five (95) and eighty-five (85) degrees. This phenomenon is known as rotational IQ phase skew. Similarly, in other instances, the I clock may remain statically offset from the center of the data bit in either the negative or positive direction. For example, the I clock may remain fixed at eighty-five (85) degrees from the edge of the data bit. This phenomenon is known as static IQ phase skew. In either scenario (e.g., rotational and/or static IQ phase skew), the sampler will fail to sample the exact center of the data bit and, thus, the likelihood of bit error will increase.
Accordingly, there is a need to effectively eliminate the rotational and static IQ phase skews generated from the phase interpolation of the I and Q clocks.